1. Field of the Invention
The present invention relates to the structure of a film carrier and a method of collectively burn-in testing IC chips assembled on a base film of the film carrier by the TAB (Tape Automated Bonding) technique.
2. Description of the Background Art
FIG. 12 is a top view showing a top structure of a conventional film carrier. FIG. 13 is a bottom perspective view showing a bottom structure of the film carrier of FIG. 12 as seen through from above. The film carrier comprises a base film 101 provided with a plurality of sprocket holes 102 arranged at regularly spaced apart intervals in the longitudinal direction of the base film 101. IC chips 104 are assembled on the base film 101 by the TAB technique. A plurality of test pads 103 in corresponding relation to a plurality of pads (not shown) of the IC chips 104 are formed on the base film 101. The test pads 103 and the pads of the IC chips 104 are connected to each other through leads 106 formed on the top surface of the base film 101, respectively. All of the test pads 103 are connected to an interconnect line 105 formed on the top surface of the base film 101. The interconnect line 105 is provided for electroplating the leads 106 and generally known as a plating line. A predetermined potential is applied from the interconnect line 105 through the test pads 103 to the leads 106 in a predetermined metal solution to electroplating the surfaces of the leads 106 for improvements in corrosion resistance of the leads 106.
For mounting the IC chips 104 on a circuit board, the leads 106 are severed at some midpoints, and the severed leads 106 are connected to electrodes of the circuit board. In general, tests are carried out on the IC chips 104 prior to the severing of the leads 106, that is, with the IC chips 104 assembled on the base film 101. One of the tests includes a burn-in test to be conducted on the IC chips 104.
FIG. 14 illustrates a method of burn-in testing the IC chips 104. First, the film carrier is severed into pieces each including an IC chip 104, and connecting portions between the interconnect line 105 and the test pads 103 are cut off. Then, the pieces of the film carrier each of which includes an IC chip 104 are mounted in sockets 107 installed on a burn-in board 108. Next, the burn-in board 108 is loaded into a burn-in apparatus 109. Thereafter, a predetermined power supply potential and a predetermined ground potential are applied from the burn-in apparatus 109 to predetermined ones of the test pads 103.
However, such a conventional film carrier is disadvantageous in that the burn-in testing of the IC chips assembled on the base film requires the burn-in board and the sockets, to result in increased costs.
Further, it takes time to mount the severed pieces of the film carrier each including an IC chip into the sockets. This causes prolonged time for preparation for the burn-in test.
Additionally, the limited capacity of the burn-in apparatus imposes limitations on the number of burn-in boards to be loaded in the burn-in apparatus at one time and accordingly on the number of IC chips to be subjected to the burn-in test at one time.